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A size of silicon wafer approximately 8 inches in diameter. Also used to refer to a tool designed to process wafers of this size.
A size of silicon wafer approximately 12 inches in diameter. Also used to refer to a tool designed to process wafers of this size.
An alternative term for the UHD digital video format.
A process where toxic or other hazardous substances are removed from a liquid or gas. Examples include removing copper particles from CMP slurry or converting liquid or gaseous toxic effluents into safe forms for disposal.
In ion implantation, a device used to increase the energy of an atom or molecule. (See Extraction Electrode)
An impurity in a semiconductor that accepts electrons. Boron is the primary acceptor used to dope silicon in the ion implantation process.
A storage unit used to temporarily store work-in-progress in a manufacturing line.
In ion implantation, the process by which atoms are introduced into a portion of a transistor to modify its material properties; in the most common application, dopant atoms become electrically active, i.e. a charge carrier is created and the conductivity of the implanted region is increased.
When dopant atoms are implanted, the silicon crystal lattice is disrupted, or amorphized. The lattice is subsequently repaired using RTP, during which process the dopant ions occupy substitutional sites in the lattice and a charge carrier is created.
ACTIVE MATRIX OLED DISPLAY (AMOLED)
A type of display that uses an array of electroluminescent OLED pixels controlled by thin-film transistors.
Each pixel of an AMOLED display produces light directly, unlike a TFT-LCD where the entire display is illuminated from behind by a backlight and selectively allowed through by thin-film transistors controlling the polarization of the liquid crystal at each pixel.
The key benefit of AMOLED displays compared to TFT-LCDs is that because "off" pixels consume no power, the overall power consumption is significantly lower.
ADVANCED BINARY MASK
A type of binary photomask that uses an opaque MoSi layer as the light-absorbing layer. An extremely thin Cr layer is placed on top and used as a hard mask for the etch process. Also called an opaque MoSi on glass (OMOG) photomask.
ADVANCED PROCESS CONTROL (APC)
A broad term referring to process control tools used for solving multivariable control problems or discrete control problem. These tools include statistical process control, run-to-run control and fault detection and classification.
ALD (ATOMIC LAYER DEPOSITION)
A thin film deposition technique where material is deposited a fraction of a monolayer of material at a time.
ALPS (ADVANCED LOW-PRESSURE SOURCE)
A PVD process performed at low pressure and large target-to-wafer distance to create a directional flux of deposited species.
ALTERNATING APERTURE PHASE SHIFT MASK (AAPSM or alt-APSM)
A type of PSM that has regions of the quartz substrate etched to different depths so as to introduce a 180 degree phase shift in the transmitted light to improve the contrast and thus the resolution of the projected image on the wafer.
Aluminum pathways within a microchip that make connections between the transistors and other circuit elements.
Disruption of the crystal lattice structure of a material due to ion implantation. The lattice can be repaired using RTP. In the pre-amorphization technique, the lattice is intentionally disrupted before implantation.
AMORPHOUS SILICON (a-Si)
A type of silicon deposited without a crystal structure.
In PV, amorphous silicon is an important thin film technology.
In LCD manufacturing, a-Si is the most widely used backplane type.
In ion implantation, a magnet used to analyze ion species and select the desired ions based on atomic weight.
A unit of length; one ten-billionth of a meter.
A high- temperature processing step designed to repair defects in the crystal structure of the wafer or induce phase transformations.
APC (AUTOMATED PROCESS CONTROL)
see advanced process control.
In ion implantation, an opening through which an ion beam is directed that defines the shape and size of the beam going forward.
APF (ADVANCED PATTERNING FILMS)
A family of strippable amorphous carbon films used as a hardmask for advanced lithography and etch patterning.
ARC (ANTI-REFLECTIVE COATING)
A light-absorbing layer (typically titanium nitride), deposited on top of metal or polysilicon, to improve lithography performance.
The ratio of depth to width of a circuit feature such as a via or contact.
ATTENUATED PHASE SHIFT MASK (APSM)
A type of PSM that allows a small amount of light to be transmitted through certain regions to interfere with the light coming from transparent parts of the mask, with the goal again of improving the contrast on the wafer.
In PV module manufacturing, an autoclave is used to remove trapped air and improve adhesion between laminating film and glass substrates by subjecting the module to elevated temperature and pressure.
AUTOMATED MATERIAL HANDLING SYSTEM (AMHS)
Any equipment that has a carrier transfer robot that moves cassettes, pods, or FOUPs to and from stationary equipment.
AUTOMATIC DEFECT CLASSIFICATION (ADC)
A technique employed by wafer inspection systems whereby defects are placed into several categories based on their physical and optical properties.
A metallic layer that covers the entire back surface of a solar PV cell and acts as a conductor.
Also used to refer to advanced cell designs such as EWT where both terminals of the cell are located on the back side of the wafer, thus increasing the light-gathering area of the cell and hence improving conversion efficiency.
The bottom layer of a thin film solar module, which provides rigidity and electrical insulation. Current is extracted from the module through the junction box that is attached to the circuit through a hole in the back glass.
In TFT-LCD manufacturing, the backplane is the array of thin-film transistors that control the light output of each pixel on the display.
There are three major backplane technologies described by the material used to make the transistor channel: amorphous silicon, metal oxide and low-temperature polysilicon.
The technique of accelerating the degassing of surfaces of a vacuum system or a component by heating during the vacuum pumping process. Used to reduce the time taken to reach UHV pressures.
BALANCE OF SYSTEM (BOS)
The components in addition to solar modules necessary to make a functioning solar PV generating system, including a mounting structure, cabling, inverters, land and maintenance.
A physical layer designed to prevent intermixing of the layers above and below the barrier layer.
A process sequence that treats more than one wafer simultaneously, as opposed to single-wafer (serial) processing.
A stationary cooled metal plate on a high current ion implanter that captures the ion beam during overscan.
In ion implantation, any undesirable species or ion charge in the ion beam.
BEAM CURRENT (IB)
The scan current in the end station of an ion implanter, defined as the product of the number, velocity and charge of the species in the beam.
In ion implantation, a negatively charged electrode used to reflect slow-moving, positively-charged ions. (See Electrostatic Mirror)
The components of the ion implanter through which the dopant beam passes under high vacuum from the source to the end station where the wafer is located.
BEOL (BACK-END OF LINE)
The series of process steps after transistor fabrication through completion of the wafer, prior to electrical test. Also known as the back-end of semiconductor manufacturing. The term back end is also used to refer to those parts of chip manufacturing after the wafer is complete, i.e. dicing, packaging and test.
In LED manufacturing, the proportion of devices made on wafer that meet the desired specification for wavelength, luminous efficacy and forward voltage.
A photomask covered with a pattern defined with a light-absorbing film, typically of chromium. Optically, this is the simplest type of photomask, lacking the phase-shifting features of PSM and APSM types. See also Advanced Binary Mask.
A measure of how closely packed memory cells are in a given area of the substrate of a memory device.
Generally speaking, higher bit density is desirable because it tends to increase performance and decrease cost-per-bit.
Typically measured in bits per square inch.
Lines through which information is written/read to/from memory cells.
Shoe covers worn to reduce contamination in a cleanroom.
A parameter used in deposition to describe the ability of a process to deposit material in the bottom of circuit features compared to the top surface of the wafer, or field. It is defined as the ratio of the film thickness on the field divided by the film thickness at the bottom of a given feature.
BPSG (BOROPHOSPHOSILICATE GLASS)
An amorphous insulating material made by doping SiO2 with boron and phosphorus to improve moisture resistance and reflow characteristics.
A defect inspection technique that collects light reflected from a defect, creating an image in which a defect appears dark against a white background. Generally speaking, brightfield systems are more sensitive, but slower than darkfield inspection. Brightfield inspection is typically used to find patterning defects during transistor fabrication.
A total-body garment worn by personnel in a cleanroom to reduce release of particles and contaminants into the air.
In a thin film PV module, relatively large conductive ribbons that collect power from individual solar cells.
The degree to which a material can store an electrical charge.
An electrical component used to temporarily store a charge. It consists of two conducting surfaces separated by a non-conducting dielectric.
An electron or hole that carries electric charge through a conducting or semiconducting material.
A measure, typically specified in cm2/V·s, of how rapidly a charge carrier (an electron or hole) can move through a semiconductor in response to an applied electric field. The conductivity of a material is proportional to mobility multiplied by the concentration of carriers. High mobility is highly desirable in semiconductor devices because it leads to higher device performance through faster transistor switching.
A metal or plastic open container used for transporting wafers (usually 25) to and from a tool. Cassettes protect wafers from damage that could be caused by direct handling.
CD-SEM (CRITICAL DIMENSION SCANNING ELECTRON MICROSCOPE)
A type of scanning electron microscope used to measure critical dimensions.
A category of thin-film solar cells that uses a cadmium-tellurium compound as the light-converting active layer.
CDU (CRITICAL DIMENSION UNIFORMITY)
a parameter used in etch to describe precision of the etch process. CDU is defined as the variation of the size of a repeating feature from its nominal value (CD) measured at several points across the substrate.
Computational Fluid Dynamics, a branch of fluid mechanics that uses numerical methods and algorithms to solve and analyze problems that involve fluid flows,
In a FET, the channel is the semiconducting region through which electrons flow between the source and drain terminals, as controlled by a voltage applied to the gate.
In ion implantation, channeling occurs when some ions in a beam strike the wafer between atomic lattice structures of single-crystal silicon and penetrate deeper than the other ions. Channeling is undesirable since the depth of the implant cannot be accurately calculated or controlled. Channeling can be reduced by tilting or rotating the wafer, covering its surface with a screen oxide, or pre-amorphizing the silicon.
The loss of an electron by an atomic particle to an ionized atom.
Copper Indium Diselenide: a type of thin film solar cell material that uses a compound of copper, indium, selenium. A fourth element, gallium, may also be added to the compound (CIGS) to achieve higher efficiency.
An area in a fab where the air is conditioned to remove airborne particles that could prevent the correct function of semiconductor devices.
CMOS (COMPLIMENTARY METAL OXIDE SEMICONDUCTOR)
A MOS device consisting of paired p-channel and n-channel transistors.
Also used to refer to the family of manufacturing processes used to construct integrated circuits that feature CMOS transistors.
CMP (CHEMICAL MECHANICAL PLANARIZATION)
A process that uses an abrasive, chemically active slurry to physically abrade the microscopic topographic features on a partly processed wafer so that subsequent processes can begin from a flat surface. Also referred to as chemical mechanical polishing.
An ion implantation technique that implants two species into the same region of the material in order to improve the electrical properties of the doped region, typically to improve transistor performance.
For example, non-dopant atoms, such as fluorine or nitrogen may be co-implanted with dopants such as boron to produce ultra-shallow PMOS transistor channels with improved dopant activation and a very sharp transition from the doped to the undoped regions.
A layer of an LCD flat panel display that is divided into transparent areas of red, green and blue, each of which overlays a transistor which is switched on an off to the full range of colors.
COMPUTER AIDED DESIGN (CAD)
The use of computer systems and software to aid creation, modification, or analysis of 2D or 3D designs.
COMPUTER INTEGRATED MANUFACTURING (CIM)
A manufacturing approach using computers to control the entire production process, allowing individual steps to exchange information and initiate actions.
A material that contains mobile charge carriers, such as electrons or ions.
A feature on a chip that forms the electrical pathway between the first interconnect layer and the transistor. This area is often filled with tungsten.
In RF plasma generation, refers to a waveform that is maintains a constant frequency and amplitude, as opposed to "pulsed" delivery where the supply is modulated, typically between two different amplitudes, at a frequency in the 100-1000Hz range.
An interconnect structure using copper as the conducting material, providing improved device speed and lower power consumption compared with aluminum interconnects.
COPPER SEED LAYER
A thin copper layer, usually deposited by physical vapor deposition, which acts as a wetting and nucleation layer for successful subsequent copper bulk film deposition by electrochemical plating.
CPD (CONFORMAL PLASMA DOPING)
A doping process that deposits a conformal layer of material containing the desired dopant species and then uses a thermal process to drive the dopants to a controlled depth in the underlying circuit structures. CPD provides a means to dope complex, 3D structures. Doping is traditionally performed by ion implantation, which bombards the wafer with dopant ions moving at high speed. However, this line-of-sight bombardment process cannot provide uniform doping of 3D structures. More importantly, the fast-moving ions can damage the ultra-thin semiconductor layers in cutting-edge chips. CPD is designed to solve both problems.
CRITICAL DIMENSION (CD)
In photolithography, CD is the minimum features size that is to be patterned on the wafer. In other semiconductor processes, CD is the size of a feature found at several points across the substrate used to describe the accuracy or other characteristic of a given process.
An undesirable effect whereby a signal in a circuit element, such as an interconnect line, affects the signal in another nearby circuit. In semiconductors, the coupling is usually a result of parasitic capacitance between the two circuits.
A technique used in damage engineering where the substrate is cooled to temperatures as low
Ion implantation into cooled substrates improves of amorphization properties and can reduce the formation end-of-range defects, leading to reduced leakage currents.
A type of secondary vacuum pump that captures gas molecules by cryogenically freezing and absorbing them. Cryopumps are capable of creating a very high vacuum but must periodically be regenerated, i.e. allowed to return to ambient temperature to desorb and pump away the captured gas species.
A material that has atoms arranged in an ordered periodic array.
CRYSTALLINE SILICON (c-Si)
A generic term for solar cell technology that uses a substrate of purified silicon in a crystalline structure.
CVD (CHEMICAL VAPOR DEPOSITION)
A process for depositing thin films by exposing the substrate to one or more volatile precursors, which react and/or decompose on the substrate surface.
The amount of time required for a wafer to process through an particular part of the manufacturing process.
A class of techniques using in ion implantation used to control the electrical characteristics of a semiconductor device by intentionally disrupting the silicon crystal structure.
In particular, damage engineering is used to control the depth to which dopants are diffused by adjusting ion dose rate, employing cryogenic implantation, and/or using co-implant species.
In fabricating transistor with very small geometries, damage engineering is used to enable performance-enhancing techniques such source-drain extensions, pre-silicide and strain engineering.
A means of creating copper metal interconnects by over-filling trenches in the interlayer dielectric using ECD then using CMP to remove the excess copper.
DARC (DIELECTRIC ANTI-REFLECTIVE COATING)
A non-reflective, non-energy-absorbing, inorganic dielectric layer deposited on top of metal or polysilicon to improve lithography performance.
A defect inspection technique that uses detectors that collect scattered light to make a defect appear bright against a dark background. Typically used to find particles on wafers during interconnect fabrication. Compare with brightfield inspection.
DEEP ULTRAVIOLET (DUV)
The portion of the ultraviolet light spectrum with wavelengths below 300nm.
A process where defects are located on a patterned wafer. A list of defect locations is created and passed to a DR-SEM for review and classification.
DEFECT REVIEW SCANNING ELECTRON MICROSCOPE (DR-SEM)
A type of scanning electron microscope used to classify defect types during the wafer manufacturing process and determine whether these defects will affect chip yields.
A process used to deposit a thin layer of insulating or conductive material onto the substrate.
Rules that outline geometry and connectivity restrictions for the design and layout of integrated circuits.
In semiconductor manufacturing, the area of the silicon wafer on which a functional circuit is fabricated. Many hundreds of identical dies (alternative plurals are die and dice) are fabricated on each wafer.
Also used more specifically to refer to an insulator that may be polarized by an applied electric field. Two dielectrics commonly used in semiconductor processing are silicon dioxide (SiO2) and silicon nitride (Si3N4).
The large conical wheel on a batch processing ion implanter used for holding wafers during ion implantation. A wafer is mounted at the end of each "spoke" of the disk. As the disks spins, each wafer in turn passes through the ion beam which is scanned radially to deliver a uniform dose across each wafer.
An impurity added in controlled amounts to a material in order to modify some intrinsic characteristic, such as resistivity or melting point. The addition of a dopant to a semiconductor creates a material with predominantly negative (n-type) or positive (p-type) charge carriers depending on the dopant species.
A viscous liquid or suspension containing dopant material.
The introduction of impurities, or dopants. into the crystal lattice of a material to modify its electrical properties. To create n-type regions, arsenic (As), arsine (AsH3), phosphine (PH3) and antimony (Sb) are commonly used. For p-type regions, typical dopants are boron (B), Boron Difluoride (BF2) and Boron Trifluoride (BF3).
The total amount of dopants measured in ions/cm2 needed to give the implanted wafer the desired electrical properties.
A precision current measuring device used to calculate the total number of ions implanted into a wafer. The function is sometimes combined with uniformity monitoring.
A class of patterning techniques designed to increase the density of circuit features that can be produced on the wafer beyond what the normal limits of a particular lithography stepper. See pitch-halving and SADP.
A technique used in solar PV manufacturing where contact lines or other structures are built up in multiple, precisely-aligned screen printing operations.
Example applications of double print include the fabrication of narrower, taller contact lines and selective emitter cell types.
DPN (DECOUPLED PLASMA NITRIDATION)
a method that uses inductive coupling to generate nitrogen plasma and incorporate nitrogen into the top surface layer of an ultra-thin gate oxide to increase the dielectric constant of the gate dielectric.
DPS (DECOUPLED PLASMA SOURCE)
A type of ICP plasma source used primarily for etch applications that separates the management of plasma density and ion energy, resulting in high etch rate and minimal plasma damage to the substrate.
The output terminal of a FET.
A type of volatile computer memory where each bit is stored in a separate capacitor. Because capacitors self-discharge over time, the state of each bit must be refreshed approximately 15 times per second, hence the term "dynamic". Compare with "static" flash memory.
DRAM offers the fastest programming of any type of memory, making it highly suitable for direct connection to a microprocessor for use as main memory.
A Damascene process designed to form and fill two features with copper at once, e.g., a trench overlying a via may both be filled with a single copper deposition step.
In solar PV technology, the fraction of incident solar energy that is converted to electrical energy.
Movement of material caused by ion motion in a conductor that arises from the momentum transfer between conducting electrons and diffusing metal atoms.
ELECTROCHEMICAL DEPOSITION (ECD)
A deposition process in which metals are removed from a chemical solution and deposited on a charged surface. Also referred to as electrochemical plating, electroplating, or electrodeposition.
Performed by means of electrolysis, which is the process of separating a liquid into its different chemical parts by passing an electric current through it.
A stable subatomic particle with a negative electric charge that acts as a carrier of electricity.
In ion implantation, a source of electrons in the end station in the vicinity of the wafer, used to neutralize undesirable charge buildup from the positively-charged implant ions that could damage sensitive circuit features.
ELECTRON VOLTS (eV)
The energy gained by an electron (or proton, same size of electric charge) moving through a voltage difference of one volt. In ion implantation, eV is used as a measure of the momentum of a particle. A particle with a higher momentum will penetrate further into the semiconductor lattice than one with less momentum.
A static voltage field in which no current is flowing. In ion implantation, it refers to using voltage to bend or focus an ion beam.
A negatively charged electrode that reflects electrons - a beam filter.
EMITTER WRAP-THROUGH (EWT)
A type of advanced back contact PV cell. In the Emitter Wrap Through cell structure, a continuous emitter is diffused through thousands of laser drilled vias less than 100 µm (micrometer) in diameter taking current to the back of the cell. By eliminating the front contacts, EWT enhances light absorption and increases cell efficiency.
The area of an ion implanter where wafers are handled and processed.
END-OF-RANGE DEFECT (EOR)
Also, known as end-of-range dislocation loops, EOR defects are imperfections in the silicon crystal lattice found immediately below the interface between the amorphized and crystalline regions of the transistor channel after ion implantation.
EOR defects can be minimized using cryogenic implantation.
ENERGY PURITY MODULE (EPM)
A beamline element used in certain Varian ion implanters that simultaneously decelerates the ion beam to the final energy and filters the ion beam to remove unwanted high-energy components that can “smear” the transistor channel, leading to increased leakage current and decreased performance.
EOT (EQUIVALENT OXIDE THICKNESS)
A number used to compare performance of gate dielectric materials by indicating how thick a silicon oxide film would need to be to produce the same effect as the dielectric material being used.
A number used to compare performance of high-k dielectric MOS gates with performance of SiO2-based MOS gates. It shows thickness of SiO2 gate oxide needed to obtain the same gate capacitance as one with thicker SiO2 dielectric with higher dielectric constant k [e.g., EOT of 1 nm would result from using a 10 nm thick dielectric featuring k=39 (k of SiO2 is 3.9)].
A method of depositing, or growing, a monocrystalline film where the deposited film takes on a lattice structure and orientation identical to those of the substrate. This enables a high-purity starting point for building a semiconductor device.
EPT (EQUIPMENT PERFORMANCE TRACKING)
An APC technique that monitors processing tools to provides visual and statistical reporting tools to identify bottlenecks and improve factory performance.
A process for removing material in a specified area through a chemical reaction or physical bombardment. The process can be performed using liquid-phase (wet) etchants or under vacuum (dry) typically using a plasma to generate gas-phase reactants.
The rate at which material is removed during etch processing, typically expressed in Å/s or nm/s.
ETCH STOP LAYER (ESL)
A film layer used to restrict etch depth and protect underlying material. The ESL is chosen to be resistant to the etch chemistry being used.
EUVL (EXTREME ULTRAVIOLET LITHOGRAPHY)
A lithography technique using 13.5nm EUV illumination. It represents a significant departure from DUV lithography because all the optical elements must act in a reflective mode and the entire optical system must be kept under vacuum.
In ion implantation, the extraction electrode is used for extracting positively charged ions from the source. Ions exiting the source combine downstream to form a beam which is used to implant dopants into a silicon wafer.
Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.
FDC (FAULT DETECTION AND CLASSIFICATION)
An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.
FEOL (FRONT-END OF LINE)
The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.
FET (FIELD EFFECT TRANSISTOR)
A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.
FI (FACTORY INTERFACE)
An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.
A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.
A finFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.
The main design goal of the finFET is to reduce current leakage while the transistor is in the "off" state.
A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.
FLAT PANEL DISPLAY (FPD)
Any consumer display device, such as an LCD or AMOLED, with a planar surface, in contrast to the curved front of cathode ray tube displays.
The flow of a physical property in space, frequently also with time variation.
In LED technology, the voltage across the terminals of the LED that is required in order for the produce a specified light output. It is also the voltage below which the LED will not produce any light.
FRONT OPENING UNIFIED POD (FOUP)
A container with a stationary cassette with a front opening interface used with an automated materials handling system (AMHS). The use of FOUPs can reduce particle counts on wafers because the interior of the FOUP is isolated from the ambient fab environment.
FSG (FLUORINE-DOPED SILICATE GLASS)
An amorphous insulating material (k=approximately 3.5) made by doping SiO2 with fluorine often used in between copper interconnect layers. Also called fluorosilicate glass.
A terminal of a FET that controls the flow of current between the source and drain terminals.
Collective term for the conductive and insulating layers that comprise the gate structure in a MOSFET.
A term, short for generation, used in FPD manufacturing to describe the size of the glass substrate.
Each generation is approximately 80% larger than its predecessor.
Generation Typical dimensions (mm) Area (m²) Introduced
400 x 500
620 x 750
730 x 920
1,000 x 1,200
1,200 x 1,300
1,300 x 1,500
1,500 x 1,850
1,870 x 2,200
1,950 x 2,250
2,160 x 2,460
2,200 x 2,500
2,880 x 3,130
A procedure that includes hand washing and the donning of gloves, head coverings, masks, shoe coverings, and other specialized garments before workers enter a cleanroom.
A support area or service area immediately outside a cleanroom that allows service personnel to perform routine maintenance without entering the cleanroom itself.
A defect inspection technique that uses detectors collecting collect mid- and high-angle scattered light to make a defect appear bright against a dark background. Typically used to find small pattern defects beyond optical resolution. Compare with brightfield inspection.
A mask that is more resistant than photoresist to etching, used when higher etch selectivity is required than can be achieved using photoresist.
HDP (HIGH DENSITY PLASMA)
A plasma featuring high concentration of free electrons, and hence, high concentration of ions.
HDP-CVD (HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION)
A type of plasma-enhanced CVD performed under high vacuum and at high plasma excitation voltage in order to improve the ability to fill small high aspect ratio structures.
HIGH CURRENT IMPLANTER
A class of ion implanter which produces the highest beam currents, typically in excess of 3mA. The greater the beam current, the faster the required dose is reached, leading to higher wafer throughput. Ion energies between 1keV and 100keV are typical.
HIGH ENERGY IMPLANTER
A class of ion implanter which can produce ion energies in excess of 1MeV, enabling dopants to be implanted well below the surface of the wafer.
HIGH-BRIGHTNESS LED (HB-LED)
A class of LED that produces enough light to be used for illumination applications. Applications include backlighting for LCD displays, room illumination and automotive exterior lights. Exactly how bright an LED must be to qualify as "high-brightness" is not well defined. The simplest definition is one that is too bright to look at directly.
In semiconductors, a hole is the absence of an electron where one could exist in an crystal lattice. It can be thought of as the opposite of an electron, with a positive charge of exactly the same magnitude as an electron. If, in an electric field, an electron moves into this vacant site, the hole has effectively moved in the opposite direction.
The intelligent factory system that communicates with the equipment used in semiconductor manufacture. In semiconductors, the SECS/GEM protocol is used.
an area known to be prone to failure
ICP (INDUCTIVELY COUPLED PLASMA)
A type of plasma source in which the energy is supplied by electrical currents which are produced by electromagnetic induction, that is, by time-varying magnetic fields generally applied from outside the vacuum enclosure.
IGZO (INDIUM GALLIUM ZINC OXIDE)
A semiconducting material used to form the channel of high-performance thin-film transistors for the active layer of LCDs. Compared to amorphous silicon, the conventional channel material, the higher electron mobility of IGZO allows the transistors to switch more rapidly, enabling higher-resolution displays with a faster refresh rate.
A lithography resolution enhancement technique that replaces the usual air gap between the final lens and the wafer surface with a liquid medium such as water.
An abbreviation for ion implantation.
In ion implantation, the incident angle between the ion beam and the wafer surface.
The examination of a wafer to detect defects of various types (e.g., scratches, particles, damaged features) following each step in the semiconductor fabrication process flow.
Nonconductive materials used to isolate electrically active areas of the device or chip from one another. Some commonly used insulators are silicon dioxide, silicon nitride, BPSG, and PSG.
INTEGRATED CIRCUIT (IC)
An electronic device that consists of many elements fabricated together on a single silicon substrate.
The wiring in an integrated circuit that connects the transistors to one another and to external connections.
INTERLAYER DIELECTRIC (ILD)
Films used between metal layers of an IC for insulation.
INTERMETAL DIELECTRIC (IMD)
Insulating films used between adjacent metal lines.
A device to convert DC power from solar panels, for example, to AC power compatible with grid electricity.
an electrically charged atom or group of atoms formed by the loss or grain of one or more electrons
A process technology in which ions of dopant chemicals (boron, arsenic, etc.) are accelerated in intense electrical fields to penetrate the surface of a wafer, thus changing the electrical characteristics of the material.
A tool designed to inject selected dopant atoms uniformly across a substrate to a prescribed depth at a desired concentration. The technique is referred to as ion implantation.
In ion implantation, an assembly that expels positive ions from a discharge by a negatively biased extraction electrode. The resulting ions can then be accelerated in a beamline towards a target wafer.
The process of adding to or removing one of more electrons from an electrically neutral atom or molecule. Once a particle is ionized, it can be accelerated, steered and otherwise manipulated using magnetic or electrostatic fields, as in a beamline.
ITO (INDIUM TIN OXIDE)
A common TCO material.
The interface between two semiconductor regions of differing dopant types. Usually refers to a p-n junction, at which the conductivity type changes from p-type to n-type.
In solar modules, an environmental enclosure designed to provide a connection point for the output of the module.
Also known as dielectric constant, often denoted by the Greek letter kappa (κ). An expression of the extent to which a material concentrates electric flux.
In electronics, it refers to the capacitance of a material relative to silicon dioxide.
A high k-value allows a transistor gate to be made smaller without increasing undesirable leakage.
A low k-value is desirable in an insulating material such as one used to separate interconnects because it reduces charge build-up which wastes energy as heat, reducing the overall power consumption of a device. In addition, a low k-value allows faster signal propagation and thus faster switching speeds.
The amount of material loss during a cutting process. In silicon wafer production, kerf loss refers to the amount of silicon consumed as part of the wafering process and plays a vital role in determining the cost, edge quality, and surface finish of a wafer.
In chemistry, a term applied to something constantly undergoing or likely to undergo change. For example, if a molecule exists in a particular conformation for a short life-time, before adopting a lower energy conformation, the former molecular structure is said to have 'high lability.' In semiconductors, it can refer to an ALD precursor chemical that reacts readily with the materials on the surface of the wafer.
A technique that uses lasers to ablate the surface of a thin film PV cell in order to define interconnect patterns.
The orderly arrangement of atoms in a crystalline solid.
LED (LIGHT-EMITTING DIODE)
A semiconductor device that emits light when an electric current flows through it. An LED consists of a p-n junction which is constructed in such a way that a photon of light is emitted when a pair of charge carriers recombine.
A parameter chiefly used in photomask etch that measures the precision of the etch process. Linearity is defined as the range of deviation from target CD across a specified range of features sizes.
The width of a metal interconnect line.
LIQUID CRYSTAL DISPLAY (LCD)
A type of flat panel display that uses an array of backlit thin film transistors called a backplane to control each pixel.
An LCD works by individually controlling each transistor to allow or block the light from a backlight. The white light then passes through an array of color filters to assemble the final, full-color image.
When a pixel transistor is turned off, the liquid crystal material rotates polarized light through 90°, allowing it to pass through the second polarizer.
When the transistor is energized, the liquid crystal molecules align in such a way that the light is no longer rotated, so the light is blocked by the second polarizer.
Any technique that enhance the resolution, fidelity or other aspect of the lithography process.
The transfer of a pattern or image from one medium to another, such as from a photomask to a wafer using a stepper.
A chamber used to transfer a wafer or wafers between the atmospheric pressure of the FI and the vacuum environment used for processing.
A batch of wafers of identical characteristics that are processed at the same time. Lots are typically kept together in FOUPs.
LOW PRESSURE CVD (LPCVD)
A CVD process performed in an environment below atmospheric pressure.
LSI (LARGE SCALE INTEGRATION)
A chip with between 3,000 and 100,000 transistors on a single die. The first LSI chips were produced in the mid- 1970s.
LTPS (LOW TEMPERATURE POLYSILICON)
A process used to create polysilicon films using a two step process. The first step deposits a precursor film at 400-450° using a PECVD process, lower than the 600-1000° LPCVD process typically used in semiconductor manufacturing. The second step uses an anneal process to convert the precursor into polysilicon.
LTPS films are commonly used in AMOLED and ultra-high resolution TFT-LCD displays.
In LED technology, a measure of how efficiently an LED converts energy to electromagnetic radiation. Usually expressed in lumens per watt (lm/W).
A patterned layer of material used to prevent the etching of the material directly beneath it. Also an abbreviation of PHOTOMASK.
MASS ANALYZER MAGNET
The mass analyzing magnet in Varian implanters is positioned between the source and the process chamber to deflect and filter ions so only selected ions enter the process chamber. This ensures that only the required dopants reach the wafer.
MATERIAL CONTROL SYSTEM (MCS)
A computer controlled system which manages the transporting and storing of work in progress material in a manufacturing environment.
MEDIUM CURRENT IMPLANTER
A class of ion implanter designed for maximum dose uniformity. Beam currents range from 1µA to 5mA, at energies from 5-600keV. Medium current implanters usually have the ability to implant dopants at implant angles down to 30° from the wafer surface, enabling dopants to be implanted partially underneath existing structures on the wafer surface.
MEMS (MICROELECTROMECHANICAL SYSTEMS)
Very small mechanical or electromechanical devices such as sensors and actuators fabricated using modified semiconductor device fabrication techniques.
MES (MANUFACTURING EXECUTION SYSTEM)
A software control system for managing and monitoring work-in-process material in a manufacturing environment.
A type of TFT-LCD backplane that uses a metallic oxide, such as IGZO, to form the transistor channel.
An alternative term for emitter wrap-through, a type of advanced back contact PV cell.
The CVD or PVD deposition of a layer of high-conductivity metal used to interconnect devices on a chip. Metals typically used include aluminum, tungsten and copper, etc.
The science of measurement to ascertain dimensions, quantity, or capacity; the techniques and procedures for using sensors and measurement equipment to determine physical and electrical properties in wafer processing.
MICRO-CRYSTALLINE SILICON (µc-Si)
A form of thin film silicon with very small (0.5-2µm) silicon crystals intermixed with amorphous silicon. It is usually deposited in a thin layer (typically 1-3µm) for tandem (stacked) thin film solar cells.
The phenomenon by which identical features are etched at different rates depending on their density (e.g. dense, semi-dense) with respect to open area features.
(µm or micrometer) A unit of length; one-millionth of a meter.
An integrated circuit that contains arithmetic, logic and control circuitry in a single package.
An enclosure or the environment created by an enclosure to keep wafers free of contamination such as a FOUP.
MOCVD (METAL-ORGANIC CHEMICAL VAPOR DEPOSITION)
MOCVD is a type of epitaxy process used to deposit compound semiconductor films, especially those used in the manufacture of high-brightness LEDs and power electronics. In an MOCVD process, a chemical reaction takes place at the surface of a substrate between organic compounds that contain the required metals and other elements.
The solar module is the final packaged PV generator. In c-Si technologies, the module typically contains several dozen solar cells wired together.
See crystalline silicon.
MOS (METAL OXIDE SEMICONDUCTOR)
a structure obtained by growing a layer of silicon dioxide (SiO2) on top of a silicon substrate and then depositing a layer of metal or polycrystalline silicon (the latter is commonly used). Often used to describe a transistor fabricated in this way.
A type of FET where the gate is isolated by a shallow layer of insulator. Constructed using MOS fabrication techniques.
In solar PV, a type of silicon wafer that is cast into ingots using grains of monocrystalline silicon. The ingots are then sliced into wafers and used in the manufacturing of microchips and photovoltaic cells.
A type of defect found in flat panel displays where areas of the display exhibit uneven brightness. Also known as “clouding”.
SACVD (SUB-ATMOSPHERIC CHEMICAL VAPOR DEPOSITION)
A term coined by Applied Materials to describe CVD processes performed slightly below atmospheric pressure using TEOS/ozone chemistry.
SADP (SELF-ALIGNED DOUBLE PATTERNING)
A double patterning technique employing sacrificial sidewall spacer films to achieve pitch-halving. Also known as sidewall spacer double patterning(SSDP) or spacer defined double patterning (SDDP).
A contraction of self-aligned silicide. Salicide processing technology seeks to exploit the principle that a refractory metal deposited on a patterned silicon substrate will selectively react with exposed silicon under specific processing conditions, and will not react with adjacent materials, such as silicon oxide material. Thus, no patterning step is required.
In ion implantation, the movement of the ion beam relative to the wafer in order to cover the entire wafer surface.
A component of an ion implanter that either moves the ion beam across the wafer, or moves the wafer through the ion beam. This may be accomplished with a magnetic field, an electrostatic field or with mechanical motion.
SCANNING ELECTRON MICROSCOPE (SEM)
A microscope that uses an electron beam rather than light to illuminate the sample. The beam is scanned back and forth across the sample surface.
In crystalline silicon solar PV manufacturing, a sheet of woven material supporting a stencil with open areas through which silver paste or other materials is forced by a roller or squeegee to form a pattern on a wafer. It is analogous to the photomask in semiconductor manufacturing.
In ion implantation, a thin, sacrificial layer of SiO2 which stops stray ions entrained in the ion beam and which will be subsequently removed. In addition, the screen oxide slightly scatters the main ion beam thus prevents channeling.
SECONDARY VACUUM PUMP
Any vacuum pump which cannot exhaust directly to atmosphere, i.e. that must work in tandem with a roughing pump. Commonly used secondary pumps in semiconductors are cryopumps and turbopumps.
SECS/GEM (SEMI EQUIPMENT COMMUNICATION STANDARD/GENERIC EQUIPMENT MODEL)
A software protocol used to standardize communication between semiconductor manufacturing equipment and the host control system. It was designed to simplify factory automation by establishing a common set of instructions that would be understood by all the equipment in a fab.
A nucleation layer where the nucleation material is the same as the subsequently deposited film.
A technique used to increase the conversion efficiency of crystalline silicon PV solar cells. Selective emitters are heavily-doped regions placed precisely underneath the front metal contact lines in order to reduce electrical contact resistance and allow electricity to flow more freely. The doped regions are typically fabricated by depositing dopant paste on the surface of the wafer and then printing the contact lines on top.
The ratio of etch rates observed in two materials during etch processing. Typically used to refer to the relative etch rates of a material intended for removal and the mask, and an important metric of etch pattern fidelity.
A material whose electrical conductivity is intermediate between that of metals (conductors) and insulators (non-conductors) and can be modified physically or chemically to increase or decrease its conductivity by the addition of dopants.
A gas that readily decomposes into silicon and hydrogen, silane is often used to deposit silicon- containing compounds. It also reacts with ammonia to form silicon nitride, or with oxygen to form silicon dioxide.
An anneal (sintering) process resulting in the formation of metal-silicon alloy (silicide) to act as a contact. For example, Ti deposited on Si forms TiSi2 as a result of silicidation.
A compound of silicon with a more electropositive element. Nickel, tantalum, titanium and cobalt silicide films are used to create ohmic (low-resistivity) contacts for transistor connections. Molybdenum silicide is commonly used as a light-absorbing layer in photomasks. Tungsten silicide (polycide) is used for DRAM gate electrodes.
SILICON DIOXIDE (SiO2)
The most common dielectric material used in semiconductor manufacturing, due to its versatility and stability. Also known simply as "oxide", it can be grown direction on silicon wafers via thermal oxidation or deposited via PECVD or HDP-CVD processes.
SILICON NITRIDE (Si3N4)
A silicon/nitrogen film dielectric deposited using plasma-enhanced or LPCVD. Sometimes loosely referred to as SiN.
A PV cell constructed with a single p-n junction. This includes amorphous silicon thin film and most crystalline silicon cell types.
SIP (SELF-IONIZED PLASMA)
A high-power magnetron source for PVD processes which imparts sufficient energy to the plasma such that the sputtered metal atoms are ionized. The metal ions can then be accelerated towards the wafer using an electric field, creating a more directional deposition pattern and thus higher step coverage in small geometry structures.
In semiconductors, a suspension of abrasive solids in a liquid used for CMP processes. In PV, used as the abrasive medium in a wire saw for wafering.
SMO (SOURCE-MASK OPTIMIZATION)
Source-mask optimization (SMO) is a resolution enhancement technique used in lithography to compensate for image errors due to aberrations, diffraction or process effects.
The use of a layered silicon-insulator-silicon substrate in semiconductor manufacturing. SOI substrates provide reduced parasitic capacitance between adjacent devices in an integrated circuit as compared to devices built into bulk wafers, enabling reduced power consumption and thus higher device performance.
A device that converts the energy of sunlight directly into electricity by the photovoltaic effect. Multiple cells are wired together to form modules.
A utility-scale photovoltaic power station.
The input terminal of an FET.
In ion implantation, the source of the desired dopant species that are processed into a plasma from which the ion beam is extracted.
In plasma processes such as etch, the energy source that is used to create and sustain the plasma in the reaction chamber.
A lightly-doped region extending from the source or drain into the transistor channel designed to spread out the electrical field during operation of a transistor device. Without the extension, the electric fields in very small transistors may be sufficient to damage the gate dielectric and cause device failure.
The ion implantation process used to create the source-drain extension is an example of damage engineering.
SPC (STATISTICAL PROCESS CONTROL)
A method for improving quality control in manufacturing by applying statistical techniques to the monitoring and control of a process.
A stationary cooled metal plate, located on top of an implant disk, that captures the ion beam during overscan.
When different recipes are used within a lot for experimental purposes to improve the performance of a particular process step, the lot is referred to as a split lot.
A method of depositing a film where atoms are ejected from a solid target material due to bombardment of the target by energetic particles.
In PV wafer manufacturing, the process of cutting silicon ingots into rectangular blocks using a specialized wire saw. The squared blocks, or bricks, are then sliced into individual wafers in the wafering process.
SRAM (STATIC RANDOM ACCESS MEMORY)
A type of computer memory where each bit is stored in a network of usually 6 or 8 transistors which has two stable states.
SRAM cells are complex and consume more area on a chip than DRAM cells, but are much faster and more power-efficient.
Microprocessors and other logic chips are often fabricated with SRAM cells on die for use as cache memory, used to store the most frequently accessed instructions and data.
SRU (SLURRY RECOVERY UNIT)
A machine used in wafering and CMP that processes used slurry in order to recover material such as abrasives and cooling for subsequent recycling.
The ratio of thickness of film on the sides of a feature to the thickness of the film at the bottom (e.g., in a via) or over the top of a feature (e.g., fins of a FinFET) respectively.
Equipment used to transfer a reticle (photomask) pattern onto a wafer. The same pattern is transferred onto each die on the wafer.
STI (SHALLOW TRENCH ISOLATION)
A technique to isolate each transistor or memory cell from its neighbors in order to prevent current leakage. The technique employs a pattern of trenches etched in the silicon, filled with an insulating material such as silicon dioxide.
Processes used in semiconductor manufacturing that introduce stress into transistors and memory cells by distorting the crystal lattice. In logic, this enables electricity to move more easily through the transistor, increasing transistor performance. In memory, strain can also reduce leakage current, allowing higher cell densities.
A kind of cutting wire used in wire saws that is formed, or crimped, into a sawtooth or similar profile in order to increase cutting speed.
The material upon which thin films are manipulated. Silicon is most commonly used for semiconductors and c-Si PV cells. Glass is commonly used for LCD and thin film PV applications.
A solar PV cell type that uses multiple light converting materials to increase conversion efficiency. Tandem junction thin film silicon cells, for example, use amorphous silicon and microcrystalline layers.
In PVD, the target is the source of the material to be deposited. Atoms are ejected from the target as a result of the bombardment of energetic particles.
TCO (TRANSPARENT CONDUCTIVE OXIDE)
Doped metal oxide films used in optoelectronic devices such as flat panel displays, touch panels and photovoltaics. In LCDs, TCO layers form the electrodes that generate the electric field to polarize the liquid crystal. In touch panels, TCO layers are used for the sensing electrodes. In PV, the TCO forms the top electrode of the cell.
TEM (TRANSMISSION ELECTRON MICROSCOPE)
A transmission electron microscope that transmits a beam of electrons through an ultra-thin specimen. It operates on the same basic principle as the optical microscope but with much higher resolution.
A liquid source for oxide deposition, Tetraethyl orthosilicate is the chemical compound with the
The terminal effect is a phenomenon in electrochemical deposition whereby the deposited film tends to be thicker at the edge of the wafer than the center. It stems from a voltage drop that occurs from where the negative terminal contacts the wafer edge towards the center, due to the resistance of the wafer. A primary component of this resistance is the seed layer which is deposited on the wafer by PVD before the plating process. The seed layer becomes thinner at each technology node, which increases the resistivity of the wafer and exacerbates the terminal effect. The effect can be compensated for by using an advanced current density control system that can modulate the applied voltage across the wafer, resulting in uniform deposition across the wafer.
TFT-LCD (THIN-FILM TRANSISTOR LIQUID CRYSTAL DISPLAY)
A type of LCD display that uses a thin-film transistor located at each pixel to directly drive the polarization of the liquid crystal, and thus control whether that pixel is on and off.
A layer of material ranging from fractions of a nanometer to several micrometers thick.
THIN-FILM TRANSISTOR (TFT)
A MOSFET manufactured with thin film technology, used primarily in the manufacturing of active matrix LCDs.
THROUGH-SILICON VIA (TSV)
A type of interconnect used in wafer-level packaging. A TSV is a vertical electrical connection, or via, that passes completely through the substrate to pass electrical signals between stacked die.
The number of wafers a tool can process per hour.
In ion implantation, the angle at which the ion beam strikes the wafer measured from perpendicular. See also orient angle.
A term used to refer to a piece of semiconductor processing equipment.
In semiconductor, non-planarity generated by the fabrication of features on the wafer surface. This can have significant effects on the patterning of subsequent layers because the limited depth of field of the stepper optical system may cause parts of the pattern to be out of specification. Also used to describe non-uniformity induced by different material removal rates in CMP.
An type of computer interface that detects the presence of a stylus or finger on a typically rectangular area.
Often integrated with a display to produce a touch screen.
A type of display, such as an TFT-LCD or AMOLED that incorporates a touch panel to enable the user to interact directly with the displayed image rather than indirectly via a mouse or trackball.
A tool that integrates several steps needed to process photoresist (deposition, soft bake, exposure, developing, hard bake) in semiconductor manufacturing.
A semiconductor device used to switch and amplify electronic signals that serves as the basic element of a integrated circuit.
A groove etched in a wafer to be used as part of a device structure.
A capacitor built into a trench on the substrate. This technique allows capacitance can be increased without increasing the area on the wafer needed to form the capacitor.
TURBOMOLECULAR PUMP (TURBO PUMP)
A type of secondary vacuum pump used to create a high vacuum. High speed turbine blades, alternating with stationary blades, compress gas molecules to the bottom of the pump for removal by a roughing pump.
ULTRA HIGH DOSE IMPLANTER
See Conformal Plasma Doping.
ULTRA-HIGH DEFINITION (UHD)
A digital video format with a resolution of 3840 x 2160 pixels.
Also known as 2160p and 4K, UHD has four times as many pixels as conventional HD 1080p video.
ULTRA-SHALLOW JUNCTION (USJ)
An area of semiconductor manufacturing that is focused on reducing the thickness of the junctions that form the source and drain regions of advanced transistors in order to improve performance while maintaining acceptable leakage current and breakdown voltage.
Deposition process in flip-chip packages that connects the die to the substrate with solder bumps.
USG (UNDOPED SILICATE GLASS)
An insulating film often used for PMD and ILD applications typically deposted using SACVD or HDP-CVD.
A pressure below atmospheric ambient, often referred to by specific pressure ranges:
Rough vacuum, from atmosphere to 1 x 10-3 Torr
High vacuum, from to 1 x 10-3 Torr to 1 x 10-9 Torr
Ultra-high vacuum (UHV) – below 1 x 10-9 Torr
In ion implantation, a device used to convert solid state ion source material into a gaseous state for ion beam production.
Vertical pathways through dielectric layers that make electrical connections between interconnect layers.
VLSI (VERY LARGE SCALE INTEGRATION)
A chip with between 10,000 and 1,000,000 transistors on a single die. The term is often extended to describe chips with any number of transistors greater than 10,000. Other terms such as ultra-large scale integration (ULSI) were coined, but are no longer in widespread use.
VNAND (VERTICAL NAND)
Also known as 3D NAND array.
A class of flash memory architectures where multiple two-dimensional arrays of memory cells are layered vertically on a single substrate (as opposed to stacking using wafer-level packaging).
VNAND is a method of increasing bit density without necessarily decreasing the size of each individual cell.
The thin, circular or nearly square slices of mono- or multicrystalline silicon on which semiconductors and PV cells are built.
The technology of combining several ICs on separate die together to form a single functional device.
The process of dividing silicon ingots or bricks into wafers.
In ion implantation, a rectangular vacuum duct located in the analyzer magnet region through which the beam passes.
A protective liner made of metal or graphite installed inside the waveguide. Unwanted ion species give up their energy on these liners.
Another name for roll-to-roll coating technology, where thin films of material are deposited on rolls of flexible material.
A process for removing unwanted material or contaminants from substrates using liquid chemistry between process steps.
Ability to spread out evenly over a solid surface instead of forming discrete droplets.
A machine that uses a moving wire to perform three key steps in the manufacture of silicon wafers.
Cropping - removing the tapered ends of monocrystalline silicon ingots
Squaring - turning the cylindrical cropped ingot into rectangular blocks, or bricks. In polycrystalline wafer manufacturing, this step is used to cut large cast ingots into bricks
Wafering - cutting the bricks into individual wafers
Connection between gates of all transistors in a certain row of a memory array segment.
Watt peak, a solar industry unit for the power of a solar cell delivered under ideal irradiation conditions.
The percentage of product (e.g. wafers or die) produced in a process that conforms to specifications.